The present invention relates generally to integrated circuit (IC) design, and more particularly to voltage level shifter designs.
In a deep submicron technology for a typical IC chip, device feature sizes, such as gate oxide thickness and channel length, have greatly reduced. In order to work with such small geography devices, the power supply voltage have to be lowered, otherwise the gate oxide may breakdown and the transistor channel may punch through. For instance, for a 90 nm technology, the power supply voltage is about 1.0V. However, in a system level, i.e., outside the IC chip, a power supply voltage may still be 2.5V or 3.3V. In order to allow such deep submicron IC chip to properly work in the high voltage system, voltage level shifters have to be employed to shift an external high voltage signal to a corresponding internal low voltage signal, and to shift an internal low voltage signal to a corresponding external high voltage signal.
FIG. 1 is a schematic diagram illustrating a conventional low-to-high voltage level shifter 100. The voltage level shifter 100 comprises a pair of PMOS transistors 112 and 116, a pair of NMOS transistors 122 and 126, and an inverter 130. These devices are connected as a cross-latch. Specifically, the PMOS transistor 112 and the NMOS transistor 122 are serially connected between an external power supply VCCH and a ground VSS, so are the PMOS transistor 116 and NMOS transistor 126. A gate of the PMOS transistor 112 is connected to the common drain of the PMOS transistor 116 and the NMOS transistor 126. A gate of the PMOS transistor 116 is connected to the common drain of the PMOS transistor 112 and the NMOS transistor 122. An input node IN is connected to a gate of the NMOS transistor 122, and to a gate of the NMOS transistor 126 through the inverter 130. An output node OUT is connected to the common drain of the PMOS transistor 116 and the NMOS transistor 126. A skilled in the art would immediately recognize that the voltage level shifter 100 functions as a two serially connected inverters from the input IN and output OUT point of view. For instance, when the input node IN is at a logic HIGH, the NMOS transistor 122 and the PMOS transistor 116 will be turned on, and the NMOS transistor 126 and the PMOS transistor 112 will be turned off, thus the output node OUT will be at the logic HIGH. However, the input node IN operates at an internal voltage between the VSS and a VCCL which is lower than the VCCH, while the output node OUT operates at an external voltage between the VSS and the VCCH. PMOS transistors 112 and 116 and NMOS transistors 122 and 126, exposing to the VCCH, are high voltage transistors with thick gate oxide, etc. The inverter 130, exposing only to the VCCL, is made of low voltage transistors with thin gate oxide, etc. With a proper adjustment of the threshold voltages of the NMOS transistors 122 and 126, the voltage level shifter 100 can achieve a voltage transition point around VCCL/2. In a static state with the node IN either at the logic HIGH or LOW, either the PMOS transistor 112 or the NMOS transistor 122 is off, and similarly, either the PMOS transistor 116 or the NMOS transistor 126 is off, there is no static conduction current flowing through the voltage level shifter 100. However, during a ramping up of the internal voltage, i.e., the voltage at the node IN is between the VSS and the normal VCCL, the NMOS transistor 122 may be weakly turned on, while the PMOS transistor 112 is still not turned off. There will be active current flowing through the PMOS transistor 112 and the NMOS transistor 122. Similarly, during a ramping down of the internal voltage, there are active current flowing through the PMOS transistor 116 and the NMOS transistor 126.
Besides, some modern memory chips employ a power saving mode. That is when the internal circuit is in a non-functional state, the internal voltage VCCL is lowered to a level just enough to maintain data in the memory. By lowering the power supply voltage, the chip's power consumption can be drastically reduced. Even though the core circuit saves power in the power saving mode, conventional voltage level shifters may introduce stray current. Referring again to FIG. 1, the output node OUT of the voltage level shifter 100 is coupled to the VSS through a high voltage NMOS transistor 142. A gate of the NMOS transistor 142 is controlled by a signal POCH which is generated by the voltage detection circuit (not shown). When the VCCL is lower than a predetermined voltage, POCH is in the logic HIGH, so that the NMOS transistor 142 is turned on and clamps the node OUT to the VSS. In so doing, the output voltage maintains certain even the internal circuit is not operating.
Referring again to FIG. 1, when the node OUT is at the VSS, the PMOS transistor 112 is on. Since the internal circuit is not operating, the node IN may be floating, and very well turn on the NMOS transistor 122. Therefore, during the power saving mode, unintentional active current may flow through the PMOS transistor 112 and the NMOS transistor 122 and defeat the power saving purpose.
As such, what is desired is a voltage level shifter that has minimized power consumption.